1. Field of the Invention
The present invention relates to a comparator circuit for comparing two signals, and more particularly to a comparator circuit provided with an input offset voltage reducing circuit for compensating for the input offset voltage by making use of the voltage-storing function of capacitors.
2. Description of the Prior Art
In a comparator circuit of this kind, the accuracy of a signal comparison operation is substantially determined by the input offset voltage of an initial stage differential amplifier. For compensating the input offset voltage, it has been performed to charge a capacitor with the offset voltage during a standby period and to subtract the voltage stored in the capacitor from the output voltage of the differential amplifier to generate an offset-free output signal during the comparison period. The offset-free output signal i.e. the result of the comparison is latched by a latch circuit during the subsequent period. Usually, the latching operation of the comparison output signal and the operation of the differential amplifier are conducted alternately, and hence the latch circuit is in operation when the differential amplifier is on standby to latch the output signal which has been amplified in the previous period by the differential amplifier. In the conventional comparator circuit thus far described, the pulse period of a control signal controlling a switch circuit used when the capacitor is being charged with the offset voltage and the pulse period of a control signal controlling the latch circuit are equal but have opposite phases. As a result, the sampling period is determined by the period making the offset voltage compensating circuit set, thus making it difficult to realize a fast operation. If the time period for charging the capacitor with the offset voltage is lengthened, more specifically, the charging operation can be completely achieved to increase the accuracy, however, the sampling period is accordingly extended and its high-speed operation is resultantly lost. However, if the sampling period is shortened to aim at a higher speed, on the other hand, the time period available for charging the capacitor with the offset voltage must be shortened to produce the defect that the accuracy is reduced. This makes it impossible to provide a comparator circuit which operates both at a high speed and with a high accuracy.